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| STA328 2.1-channel high-efficiency digital audio system Features ! ! Wide supply voltage range (10 V - 36 V) Three power output configurations - 2 x 40 W + 1 x 80 W - 2 x 80 W - 1 x 160 W PowerSO-36 package 2.1 channels of 24-bit DDX(R) 100-dB SNR and dynamic range 32 kHz to 192 kHz input sample rates Digital gain/attenuation +48 dB to -80 dB in 0.5-dB steps Four 28-bit user programmable biquads (EQ) per channel I2C control 2-channel I2S input data interface Individual channel and master gain/attenuation Individual channel and master soft/hard mute Individual channel volume and EQ bypass Bass/treble tone control Dual independent programmable limiters/compressors AutoModes - 32 preset EQ curves - 15 preset crossover settings - Auto volume controlled loudness - 3 preset volume curves - 2 preset anti-clipping modes - Preset night-time listening mode - Preset TV AGC Device summary Order code Package PowerSO-36 PowerSO-36 Tube Tape and reel ! ! ! ! ! ! ! ! ! ! ! ! PowerSO-36 with slug up ! ! ! ! ! ! ! ! ! ! ! ! ! ! Input and output channel mapping AM noise-reduction and PWM frequency-shifting modes Software volume update and muting Auto zero detect and invalid input detect muting Selectable DDX(R) ternary or binary PWM output + variable PWM speeds Selectable de-emphasis Post-EQ user programmable mix with default 2.1 bass-management settings Variable max power correction for lower fullpower THD Four output routing configurations Selectable clock input ratio 96 kHz internal processing sample rate, 24 to 28-bit precision Video application supports 576 * fs input mode. Table 1. Packaging STA328 STA32813TR May 2008 Rev 4 1/57 www.st.com 1 Contents STA328 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 1.2 1.3 1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 Package pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 3.2 3.3 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 12 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 6.2 6.3 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 6.3.2 DDX(R) power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DDX(R) variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 6.5 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/57 STA328 Contents 6.6 6.7 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 6.7.2 6.7.3 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.8 AutoMode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.8.1 6.8.2 6.8.3 AutoModes EQ, volume, GC (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . 35 AutoMode AM/pre-scale/bass management scale (addr 0x0C) . . . . . . 36 Preset EQ settings (addr 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9.1 6.9.2 6.9.3 Channel 1 configuration (addr 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Channel 2 configuration (addr 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Channel 3 configuration (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.10 6.11 Tone control (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 Limiter 1 attack/release threshold (addr 0x12) . . . . . . . . . . . . . . . . . . . . 41 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 41 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 41 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 41 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 7.2 7.3 7.4 7.5 7.6 EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 47 User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 Coefficient address register 1 (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . 47 Coefficient b1data register bits 23:16 (addr 0x17) . . . . . . . . . . . . . . . . . 47 Coefficient b1data register bits 15:8 (addr 0x18) . . . . . . . . . . . . . . . . . . 47 Coefficient b1data register bits 7:0 (addr 0x19) . . . . . . . . . . . . . . . . . . . 47 Coefficient b2 data register bits 23:16 (addr 0x1A) . . . . . . . . . . . . . . . . 47 Coefficient b2 data register bits 15:8 (addr 0x1B) . . . . . . . . . . . . . . . . . 48 3/57 Contents 7.6.7 7.6.8 7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.6.14 7.6.15 7.6.16 7.6.17 STA328 Coefficient b2 data register bits 7:0 (addr 0x1C) . . . . . . . . . . . . . . . . . . 48 Coefficient a1 data register bits 23:16 (addr 0x1D) . . . . . . . . . . . . . . . . 48 Coefficient a1 data register bits 15:8 (addr 0x1E) . . . . . . . . . . . . . . . . . 48 Coefficient a1 data register bits 7:0 (addr 0x1F) . . . . . . . . . . . . . . . . . . 48 Coefficient a2 data register bits 23:16 (addr 0x20) . . . . . . . . . . . . . . . . 48 Coefficient a2 data register bits 15:8 (addr 0x21) . . . . . . . . . . . . . . . . . 48 Coefficient a2 data register bits 7:0 (addr 0x22) . . . . . . . . . . . . . . . . . . 48 Coefficient b0 data register bits 23:16 (addr 0x23) . . . . . . . . . . . . . . . . 49 Coefficient b0 data register bits 15:8 (addr 0x24) . . . . . . . . . . . . . . . . . 49 Coefficient b0 data register bits 7:0 (addr 0x25) . . . . . . . . . . . . . . . . . . 49 Coefficient write control register (addr 0x26) . . . . . . . . . . . . . . . . . . . . . 49 7.7 7.8 7.9 7.10 7.11 7.12 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Variable max power correction (addr 0x27, 0x28) . . . . . . . . . . . . . . . . . . 53 Fault detect recovery (addr 0x2B, 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4/57 STA328 Description 1 1.1 Description Overview The STA328 comprises digital audio processing, digital amplifier control and DDX(R) power output stage to create a high-power single-chip DDX(R) solution for high-quality, high-efficiency, all digital amplification. The STA328 power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge to give up to 2 x 40 W plus 1 x 80 W of power output. Two channels can be provided by two full-bridges to give up to 2 x 80 W of power. The IC can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 W output. Also provided in the STA328 is a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control. AutoModes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes auto volume loudness, preset volume curves, preset EQ settings. New advanced AM radio-interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX(R) processing are provided. This high-quality conversion from PCM audio to patented DDX(R) 3-state PWM switching provides over 100 dB of SNR and dynamic range. Figure 1. Block diagram SDA SCL I 2C l System Contro DDX-SPIRIT LRCKI BICKI SDI_12 Serial Data Input, Channel Mapping & Resampling OUT1A Audio EQ, Mix, Crossver, Volume, Limiter Processing DDX Processing (R) Quad Half-Bridge Power Stage OUT1B OUT2A OUT2B System Timing PLL TWARN FAULT EAPD Power-Down CLK Figure 2. I2 S Input Channel signal flow diagram through the digital core Channel Mapping Re-sampling EQ Processing M ix Crossover Filter Volume Limiter 4X Interp DDX(R) DDX Output 5/57 Description STA328 1.2 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, up to four user-defined biquads can be applied to each of the two channels. Pre-scaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow through the EQ block Pre Scale High-P ass Filter BQ#1 BQ#2 BQ#3 BQ#4 DeEmphasis Bass Filter T reble Filter To Mix Re-sampled Input If HPB = 0 4 Biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto Loudness if AMEQ = 10 If DEMP = 1 If CxT CB = 0 BT C: Bass Boost/Cut T T C: T reble Boost/Cut If DSPB = 0 & CxEQB = 0 1.3 Output configurations Figure 4. Output power-stage configurations Half Bridge OUT1A Channel 1 Half Bridge 2-channel (full-bridge) configuration, register bits OCFG[1:0] = 00 OUT1B OUT2A Half Bridge Channel 2 Half Bridge OUT2B Half Bridge Channel 1 OUT1A 2.1-channel configuration, register bits OCFG[1:0] = 01 Half Bridge Channel 2 OUT1B OUT2A Half Bridge Channel 3 Half Bridge OUT2B OUT1A Half Bridge Half Bridge OUT1B 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 Channel 3 Half Bridge OUT2A Half Bridge OUT2B The setup register is Configuration register F (addr 0x05) on page 31 6/57 STA328 Description 1.4 Applications Figure 5. Application circuit for 2.1/2.0 configurable solution SUB_GND 7/57 Pin out STA328 2 2.1 Pin out Package pins Figure 6. Pin connections VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG 2.2 Pin list Table 2. Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O N.C. O I/O N.C. I/O I/O I/O O O I/O I/O I/O. N.C. Pin list Type Name SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. Ground Not connected Output half bridge 2B Positive supply Not connected Negative supply Negative supply Positive supply Output half bridge 2A Output half bridge 1B Positive supply Negative supply Negative supply Not connected Description 8/57 STA328 Table 2. Number 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 I/O O I/O I/O I/O I/O I I I I/O I I I/O I/O I I/O I I/O I/O I/O I/O Pin out Pin list Type Name VCC1A OUT1A GND_CLEAN GND_REG VDD_REG VL CONFIG RESET SCL SDA RESERVED PLL_FILTER XTI GNDA VDDA SDI LRCKI BICKI GND VDD VSS VCC_SIGN Positive supply Output half bridge 1A Logical ground Substrate ground Logic supply Logic supply Logic levels Reset I2C serial clock I2C serial data This pin must be connected to GND Connection to PLL filter PLL input clock Analog ground Analog supply, nominally 3.3 V I2S serial data channels 1 & 2 I2S left/right clock, I2S serial clock Digital ground Digital supply, nominally 3.3 V 5 V regulator referred to +VCC 5 V regulator referred to ground Description 2.3 Pin description OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3) Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the speakers. RESET (pin 22) Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock. 9/57 Pin out I2C signals (pins 23 and 24) STA328 The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (Chapter 5 on page 16 gives more information). Fast-mode (400 kB/s) I2C communication is supported. GNDA and VDDA (pins 28 and 29) This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit. CLK (pin 27) This is the master clock in used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256 * fs) for a 48 kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate. FILTER_PLL (pin 26) This is the connection for external filter components for the PLL loop compensation. The schematic diagram in Figure 5 on page 7 shows the recommended circuit. BICKI (pin 32) The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64 * fs using I2S serial format. SDI_12 (pin 30) This is the serial data input where PCM audio information enters the device. Six format choices are available including I2S, left or right justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. LRCKI (pin 31) The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs. 10/57 STA328 Electrical specifications 3 Electrical specifications Table 3. Symbol VDD33 Vi Vo Tstg Tamb VCC VMAX Absolute maximum ratings Parameter 3.3 V I/O power supply (pins VDDA, VDD) Voltage on input pins Voltage on output pins Storage temperature Ambient operating temperature DC supply voltage (pins VCCnA, VCCnB) Maximum voltage on VL (pin 20) -0.5 to 4 -0.5 to (VDD33 + 0.5) -0.5 to (VDD33 + 0.5) -40 to +150 -20 to +85 40 5.5 Value Unit V V V C C V V Table 4. Symbol Rthj-case Tj-SD TWARN Th-SD Thermal data Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min Typ Max 2.5 Unit C/W C C C Table 5. Symbol VDD33 Tj Recommended operating conditions Parameter I/O power supply Operating junction temperature Value 3.0 to 3.6 -20 to +125 Unit V C 3.1 General interface specifications Operating conditions VDD33 = 3.3 V 0.3 V, Tamb = 25 C unless otherwise specified Table 6. Symbol Iil Iih IOZ Vesd General interface electrical characteristics Parameter Low level input no pull-up High level input no pull-down Test Condition Vi = 0 V (1) Min. Typ. Max. 1 2 2 Unit A A A V Vi = VDD33 (1) 3-state output leakage without Vi = VDD33 (1) pull-up/down Electrostatic protection (human-body model) Leakage current < 1 A 2000 1. The leakage currents are generally very small (< 1 nA). The values given here are the maximum values after an electrostatic stress on the pin. 11/57 Electrical specifications STA328 3.2 DC electrical specifications (3.3 V buffers) Operating conditions VDD33 = 3.3 V 0.3 V, Tamb = 25 C unless otherwise specified Table 7. Symbol VIL VIH Vhyst Vol Voh DC electrical specifications Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output High level output IoI = 2 mA Ioh = -2 mA VDD33 - 0.15 2.0 0.4 0.15 Test condition Min. Typ. Max. 0.8 Unit V V V V V 3.3 Power electrical specifications Operating conditions VDD33 = 3.3 V 0.3 V, VL = 3.3 V, VCC = 30 V, Tamb = 25 C unless otherwise specified. Table 8. Symbol RdsON Idss gN gP Dt_s td ON td OFF tr tf VCC VL VH IVCCPWRDN Power electrical characteristics Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON matching Power Nchannel RdsON matching Low current dead time (static) Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage Low logical state voltage VL High logical state voltage VH Supply current from VCC in PWRDN Supply current from VCC in 3-state VL = 3.3 V VL = 3.3 V Pin PWRDN = 0 V VCC = 30 V, 3-state 22 Test conditions Id = 1A VCC = 35 V Id = 1 A Id = 1 A See test circuits, Figure 7 and Figure 8 Resistive load Resistive load Resistive load, Figure 7 and Figure 8 Resistive load, Figure 7 and Figure 8 10 0.8 1.7 3 95 95 10 20 100 100 25 25 36 Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns V V V mA mA IVCC-hiz 12/57 STA328 Table 8. Symbol Electrical specifications Power electrical characteristics (continued) Parameter Test conditions Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters 4.5 Min. Typ. Max. Unit IVCC Supply current from VCC in operation (both channel switching) Overcurrent protection threshold (short circuit current limit) Undervoltage protection threshold Output minimum pulse width Output power (refer to test circuit Output power (refer to test circuit 80 mA Iout-sh 6 A VUV tpw-min Po 7 No load THD = 10% RL = 4, VCC = 21 V RL = 8, VCC = 36 V THD = 1% RL = 4, VCC = 21 V RL = 8, VCC = 36 V 70 50 80 40 62 150 V ns W W W W Po Figure 7. Test circuit 1 OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr, DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50% M58 INxY M57 gnd OUTxY R8W + V67 vdc = Vcc/2 DTr DTf Figure 8. Test circuit 2 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A DTout(A) M58 Q1 OUTA Rload=4 L67 10 C69 470nF DTout(B) L68 10 C70 470nF Q2 OUTB M64 Duty cycle=B DTin(A) INA DTin(B) INB Iout=1.5A M57 Q3 Iout=1.5A Q4 M63 C71 470nF Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure D06AU1651 13/57 Electrical characteristics curves STA328 4 Electrical characteristics curves Figure 9. Channel separation vs frequency +10 +0 dBr A -10 -20 -30 -40 -50 -60 -70 -80 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 10. THD vs output power - single ended 10 5 THD (%) 2 1 0.5 Vcc = 36 V RL = 4 f = 1 kHz 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 5 10 20 50 60 Po (W) 14/57 STA328 Figure 11. THD vs output power - BTL Electrical characteristics curves 10 5 THD (%) 2 1 0.5 Vcc = 36 V Rl = 8 f = 1 kHz 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 5 10 20 50 100 Po (W) Figure 12. THD vs frequency - BTL 1 0.5 THD (%) 0.2 Vcc = 36 V RL = 8 f = 1 kHz 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Hz 15/57 I2C bus specification STA328 5 I2C bus specification The STA328 supports the I2C protocol. This protocol defines any device that sends data on to the I2C bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA328 is always a slave device in all of its communications. 5.1 Communication protocol Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. Stop condition STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA328 and the bus master. Data input During the data input the STA328 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 5.2 Device addressing To start communication between the master and the STA328, the master must initiate with a start condition. Following this, the master sends 8 bits (MSB first) onto the SDA line corresponding to the device select address and read or write mode. The 7 MSBs are the device address identifiers, corresponding to the I2C bus definition. The STA328 device address is decimal 34 (binary 00100010). The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA328 identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 16/57 STA328 I2C bus specification 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA328 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address the STA328 again responds with an acknowledgement. Figure 13. I2C write procedure ACK BYTE WRITE START DEV-ADDR RW ACK MULTIBYTE WRITE START DEV-ADDR RW SUB-ADDR ACK DATA IN ACK DATA IN STOP SUB-ADDR ACK DATA IN STOP ACK ACK Byte write In the byte write mode the master sends one data byte. This is acknowledged by the STA328. The master then terminates the transfer by generating a STOP condition. Multi-byte write The multi-byte write modes can start from any internal address. Sequential data byte writes will be written to sequential addresses within the STA328. The master generating a STOP condition terminates the transfer. 5.4 Read operation Figure 14. I2C read procedure ACK CURRENT ADDRESS READ START RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START ACK SEQUENTIAL RANDOM READ START DEV-ADDR RW SUB-ADDR START ACK DEV-ADDR RW ACK DATA ACK DATA DEV-ADDR DATA NO ACK RW ACK DEV-ADDR SUB-ADDR ACK STOP ACK DEV-ADDR DATA NO ACK RW RW= ACK HIGH DEV-ADDR DATA START ACK DATA RW ACK DATA NO ACK STOP STOP ACK DATA STOP NO ACK Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 17/57 I2C bus specification STA328 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA328. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA328 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA328 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the STA328. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 18/57 STA328 Register description 6 Register description You must not reprogram the register bits marked "Reserved". It is important that these bits keep their default reset values. Table 9. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x1F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D Register summary Name ConfA ConfB ConfC ConfD ConfE ConfF Mmute Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr2 B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 D7 FDRB C2IM D6 TWAB C1IM D5 TWRB DSCKE CSZ3 DRC IR1 SAIFB CSZ2 BQL D4 IR0 SAI3 CSZ1 PSL AME D3 D2 MCS2 SAI2 CSZ0 DSPB D1 MCS1 SAI1 OM1 DEMP D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB Reserved BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 Reserved CSZ4 MME SVE EAPD ZDE ZCE PWDN Reserved PWMS ECLE Reserved MPC IDE OCFG1 Reserved BCLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved MV7 C1V7 C2V7 C3V7 AMPS XO3 MV6 C1V6 C2V6 C3V6 MV5 C1V5 C2V5 C3V5 MV4 C1V4 C2V4 C3V4 AMGC0 XO1 MV3 C1V3 C2V3 C3V3 AMV1 AMAM2 PEQ3 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 MV2 C1V2 C2V2 C3V2 AMV0 AMAM1 PEQ2 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 MV1 C1V1 C2V1 C3V1 AMEQ1 AMAM0 PEQ1 C1EQBP C2EQBP Reserved BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 Reserved AMGC1 XO2 XO1 Reserved Reserved Reserved PEQ4 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 CFA7 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 CFA6 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 19/57 Register description Table 9. Address 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D STA328 Register summary Name A1cf2 A1cf3 A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 D7 C3B15 C3B7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 D6 C3B14 C3B6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 D5 C3B13 C3B5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 D4 C3B12 C3B4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 D3 C3B11 C3B3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 D2 C3B10 C3B2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 R1 D1 C3B9 C3B1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA D0 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 Reserved Reserved FDRC8 FDRC0 Reserved Reserved Reserved Reserved Reserved RA MPCC15 MPCC14 MPCC13 MPCC12 MPCC7 MPCC6 MPCC5 MPCC4 MPCC11 MPCC3 MPCC10 MPCC9 MPCC2 MPCC1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FDRC1 FDRC2 FDRC15 FDRC7 FDRC14 FDRC6 FDRC13 FDRC5 FDRC12 FDRC4 FDRC11 FDRC3 FDRC10 FDRC2 FDRC9 FDRC1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 6.1 Configuration register A (addr 0x00) D7 FDRB 0 D6 TWAB 1 D5 TWRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1 Table 10. Bit 0 1 2 Master clock select RST 1 1 0 Name MCS0 MCS1 MCS2 Description R/W RW RW RW I2S sample frequency and the input clock. Master clock select: Selects the ratio between the input The STA328 will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. Therefore the internal clock will be: " " " 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate is determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx 20/57 STA328 Register description bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 11. IR and MCS settings for input sample rate and clock rate IR 000 32, 44.1, 48 88.2, 96 176.4, 192 00 01 1X 768 fs 384 fs 384 fs 001 512 fs 256 fs 256 fs 010 384 fs 192 fs 192 fs MCS[2:0] 011 256 fs 128 fs 128 fs 100 128 fs 64 fs 64 fs 101 576 fs x x Input sample rate fs (kHz) Table 12. Bit 4:3 Interpolation ratio select RST 00 Name IR[1:0] Description Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency R/W RW The STA328 has variable interpolation (re-sampling) settings such that internal processing and DDX(R) output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. Table 13. IR bit settings as a function of input sample rate IR[1,0] 00 00 00 01 01 10 10 1st stage interpolation ratio 2 times over-sampling 2 times over-sampling 2 times over-sampling Pass-through Pass-through Down-sampling by 2 Down-sampling by 2 Input sample rate fs (kHz) 32 44.1 48 88.2 96 176.4 192 Table 14. Bit R/W Thermal warning recovery bypass RST Name Description Thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled 5 RW 1 TWRB If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery will determine if the adjustment is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the gain adjustment determined by the thermal warning post-scale (default = -3 dB) will be removed and the gain will be added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the thermal warning post-scale gain adjustment will remain until TWRB is changed to zero or the device is reset. 21/57 Register description Table 15. Bit STA328 Thermal warning adjustment bypass RST Name Description Thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled R/W 6 RW 1 TWAB The on-chip STA328 power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400 ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, whether the gain is reapplied when TWARN is de-asserted is dependent on the TWRB bit. Table 16. Bit Fault detect recovery bypass RST Name Description Fault detector recovery bypass: 0: fault detector recovery enabled 1: fault detector recovery disabled R/W 7 RW 0 FDRB The DDX(R) power block can provide feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery). It holds it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (FDRC registers 0x29 to 0x2A), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 22/57 STA328 Register description 6.2 Configuration register B (addr 0x01) D7 C2IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0 This register configures the serial data interface Table 17. Bit 3:0 4 R/W RW RW Serial audio input interface format RST 0000 0 Name SAI[3:0] SAIFB Description Serial audio input interface format: determines the interface format of the input serial digital audio interface (see below). Data format: 0: MSB first 1: LSB first The STA328 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA328 always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 31), serial clock BICKI (pin 32), and serial data SDI (pin 30). SAI[3:0] and SAIFB are used to specify the serial data format. The default format is I2S, MSB-first. Available formats are shown below in Figure 15 and the tables that follow. Figure 15. General serial input and output formats I2S LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Left Justified LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Right Justified LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Table 18 lists the serial audio input formats supported by STA328 when BICKI = 32 * fs, 48 * fs and 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 kHz. 23/57 Register description Table 18. BICKI 32 * fs STA328 Supported serial audio input formats SAI [3:0] 1100 1110 X X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X SAIFB I2S 15-bit data Left/right justified 16-bit data I2S 23-bit data I2S 20-bit data I2S 18-bit data MSB first I2S 16-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit Data Right-justified 16-bit Data I2S 24-bit data I2S 20-bit data I2S 18-bit data MSB first I2S 16-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data Interface format 48 * fs 0100 0100 1000 0100 1100 0001 0101 1001 1101 0010 0110 1010 1110 64 * fs 0000 0100 1000 0000 1100 0001 0101 1001 1101 0010 0110 1010 1110 For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first. 24/57 STA328 Table 19. Register description Serial input data timing characteristics (fs = 32 to 192 kHz) Parameter in Figure 16 BICKI frequency (slave mode) BICKI pulse width low (T0) (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI active to LRCKI edge delay (T3) SDI valid to BICKI active setup (T4) BICKI active to SDI hold time (T5) Value 12.5 MHz max. 40 ns min. 40 ns min. 20 ns min. 20 ns min. 20 ns min. 20 ns min. Figure 16. Serial input data timing T2 T3 T1 T0 LRCKI BICKI T4 SDI T5 Table 20. Bit Delay serial clock enable RST Name Description Delay serial clock enable: 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices R/W 5 RW 0 DSCKE Table 21. Bit 6 7 Channel input mapping RST 0 1 C1IM C2IM Name Description 0: processing channel 1 receives left I2S input 1: processing channel 1 receives right I2S input 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input R/W RW RW Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 25/57 Register description STA328 6.3 Configuration register C (addr 0x02) D7 Reserved 0 D6 CSZ4 1 D5 CSZ3 0 D4 CSZ2 0 D3 CSZ1 0 D2 CSZ0 0 D1 OM1 1 D0 OM0 0 6.3.1 DDX(R) power output mode Table 22. Bit 1:0 DDX(R) power output mode RST 10 Name OM[1:0] Description DDX(R) power output mode: Selects configuration of DDX(R) output. R/W RW The DDX(R) power output mode selects how the DDX(R) output timing is configured. Different power devices can use different output modes. The recommended use is OM = 10. When OM = 11 the CSZ bits determine the size of the DDX(R) compensating pulse. Table 23. DDX(R) output modes OM[1,0] 00 01 10 11 Not used Not used Output stage - mode Recommended Variable compensation 6.3.2 DDX(R) variable compensating pulse size The DDX(R) variable compensating pulse size is intended to adapt to different power stage ICs. Contact Apogee applications for support when deciding this function. Table 24. DDX(R) compensating pulse CSZ[4:0] 00000 00001 ... 10000 ... 11111 Compensating pulse size 0 clock period compensating pulse size 1 clock period compensating pulse size ... 16 clock period compensating pulse size ... 31 clock period compensating pulse size 26/57 STA328 Register description 6.4 Configuration register D (addr 0x03) D7 MME 0 D6 ZDE 1 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0 Table 25. Bit High-pass filter bypass RST Name Description High-pass filter bypass bit. 0: AC coupling high pass filter enabled 1: AC coupling high pass filter disabled R/W 0 RW 0 HPB The STA328 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of this filter is to prevent DC signals from passing through a DDX(R) amplifier. DC signals can cause speaker damage. Table 26. Bit De-emphasis RST Name De-emphasis: 0: no de-emphasis 1: de-emphasis Description R/W 1 RW 0 DEMP By setting this bit to 1, the de-emphasis will be implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for de-emphasis to function. Table 27. Bit DSP bypass RST Name Description DSP bypass bit: 0: normal Operation 1: bypass of EQ and mixing functionality R/W 2 RW 0 DSPB Setting the DSPB bit bypasses all the EQ and mixing functionality of the STA328 core. Table 28. Bit Post-scale link RST Name Description Post-scale link: 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value R/W 3 RW 0 PSL Post-scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Post-scale can also be used to limit the maximum modulation index and therefore the peak current. A setting of 1 in the PSL register will result in the use of the value stored in channel 1 post-scale for all three internal channels. 27/57 Register description Table 29. Bit STA328 Biquad coefficient link RST Name Description Biquad Link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values R/W 4 RW 0 BQL For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. Table 30. Bit Dynamic range compression/anti-clipping bit RST Name Description Dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode R/W 5 RW 0 DRC Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. Table 31. Bit 6 Zero detect mute enable RST 1 ZDE Name Description Zero detect mute enable: setting of 1 enables the automatic zero-detect mute R/W RW Setting the ZDE bit enables the zero-detect automatic mute. When ZDE = 1, the zero detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. Table 32. Bit Miami mode enable RST Name Description Miami mode enable: 0: sub mix into left/right disabled 1: sub mix into left/right enabled R/W 7 RW 0 MME 28/57 STA328 Register description 6.5 Configuration register E (addr 0x04) D7 SVE 1 D6 ZCE 1 D5 Reserved 0 D4 PWMS 0 D3 AME 0 D2 Reserved 0 D1 MPC 1 D0 MPCV 0 Table 33. Bit Max power correction variable RST Name Description Max power correction variable: 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient R/W 0 RW 0 MPCV By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the MPCC registers (address 0x27, 0x28) it becomes possible to adjust the THD at maximum unclipped power to a lower value for a particular application. Table 34. Bit Max power correction RST Name Max power correction: 0: MPC disabled 1: MPC enabled Description R/W 1 RW 1 MPC Setting the MPC bit corrects the DDX(R) power device at high power. This mode lowers the THD+N of a full DDX(R) system at maximum power output and slightly below. Table 35. Bit AM mode enable RST Name Description AM mode enable: 0: normal DDX(R) operation. 1: AM reduction mode DDX(R) operation. R/W 3 RW 0 AME The STA328 features a DDX(R) processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX(R) is operating in a device with an active AM tuner. The SNR of the DDX(R) processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio. Table 36. Bit 4 PWM speed mode RST 0 Name PWMS Description PWM speed selection: normal or odd R/W RW Table 37. PWM output speed selections PWM output speed Normal speed (384 kHz) all channels Odd speed (341.3 kHz) all channels PWMS[1:0] 0 1 29/57 Register description Table 38. Bit STA328 Zero-crossing volume enable RST Name Description Zero-crossing volume enable: 1: volume adjustments will only occur at digital zerocrossings 0: volume adjustments will occur immediately R/W 6 RW 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Table 39. Bit Soft volume update enable RST Name Description Soft volume enable: 1: volume adjustments will use soft volume 0: volume adjustments will occur immediately R/W 7 RW 1 SVE The STA328 includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to 0. 30/57 STA328 Register description 6.6 Configuration register F (addr 0x05) D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 Reserved 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1 0 D0 OCFG0 0 Table 40. Bit Output configuration selection RST Name Description Output configuration selection 00: 2-channel (full-bridge) power, 1-channel DDX(R) is default R/W 1:0 RW 00 OCFG[1:0] Table 41. Output configuration selection Output power configuration 2 channel (full-bridge) power, 1 channel DDX(R): 1A/1B 1A/1B 2A/2B 2A/2B 2 (half-bridge) and 1 (full-bridge) on-board power: 1A 1A binary 2A 1B binary 3A/3B 2A/2B binary Reserved 1 channel mono-parallel: 3A 1A/1B 3B 2A/2B OCFG[1:0] 00 01 10 11 Table 42. Bit Invalid input detect mute enable RST Name Description Invalid input detect auto-mute enable: 0: disabled 1: enabled R/W 2 RW 1 IDE Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automatically mute all outputs if the signals are perceived as invalid. Table 43. Bit Binary clock loss detection enable RST Name Description Binary output mode clock loss detection enable 0: disabled 1: enabled R/W 3 RW 1 BCLE Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. 31/57 Register description Table 44. Bit STA328 Auto-EAPD on clock loss enable RST Name Description Auto EAPD on clock loss 0: disabled 1: enabled R/W 5 RW 0 ECLE When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. Table 45. Bit Software power down RST Name Description Software power down: 0: power down mode: initiates a power-down sequence which results in a soft mute of all channels and finally asserts EAPD circa 260 ms later 1: normal operation R/W 6 RW 1 PWDN Table 46. Bit External amplifier power down RST Name Description External amplifier power down: 0: external power stage power down active 1: normal operation R/W 7 RW 0 EAPD EAPD is used to actively power down a connected DDX(R) power device. This register has to be written to 1 at start-up to enable the DDX(R) power device for normal operation. 32/57 STA328 Register description 6.7 6.7.1 Volume control Master controls Master mute register (addr 0x06) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 Reserved 0 D3 Reserved 0 D2 Reserved 0 D1 Reserved 0 D0 MMUTE 0 Master volume register (addr 0x07) D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1 Note: Value of volume derived from MVOL is dependent on AMV AutoMode volume settings. 6.7.2 Channel controls Channel 1 volume (addr 0x08) D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0 Channel 2 volume (addr 0x09) D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0 Channel 3 volume (addr 0x0A) D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0 6.7.3 Volume description The volume structure of the STA328 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find the actual gain/volume value for any given channel. When set to 1, the master mute will mute all channels, whereas the individual channel mutes (CxM) will mute only that channel. Both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz). A "hard 33/57 Register description STA328 mute" can be obtained by programming the value 0xFF to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -100 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates will occur immediately. The STA328 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when SVE = 1 (configuration register E). This feature can be disabled by setting SVE = 0. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Also, master soft-mute will not affect the channel if CxVBP = 1. Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel Table 47. Master volume offset as a function of MV[7:0] MV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01001100 (0x4C) ... 11111110 (0xFE) 11111111 (0xFF) 0 dB -0.5 dB -1 dB ... -38 dB ... -127 dB Hard master mute Volume offset from channel value Table 48. Channel volume as a function of CxV[7:0] CxV[7:0] Volume +48 dB +47.5 dB +47dB ... +0.5 dB 0 dB -0.5 dB ... -79.5 dB Hard channel mute 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01100001 (0x5F) 01100000 (0x60) 01011111 (0x61) ... 11111110 (0xFE) 11111111 (0xFF) 34/57 STA328 Register description 6.8 6.8.1 AutoMode registers AutoModes EQ, volume, GC (addr 0x0B) D7 AMPS 1 D6 Reserved 0 D5 AMGC1 0 D4 AMGC0 0 D3 AMV1 0 D2 AMV0 0 D1 AMEQ1 0 D0 AMEQ0 0 Table 49. AutoMode EQ AMEQ[1,0] Mode (biquad 1-4) User programmable Preset EQ - PEQ bits Auto volume controlled loudness curve Not used 00 01 10 11 By setting AMEQ to any setting other than 00 enables AutoMode EQ where biquads 1-4 are not user programmable. Any coefficient settings for these biquads are ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-2 becomes hard-set to -18 dB. Table 50. AutoMode volume AMV[1,0] 00 01 10 11 Mode (MVOL) MVOL 0.5 dB 256 steps (standard) MVOL auto curve 30 steps MVOL auto curve 40 steps MVOL auto curve 50 steps Table 51. AutoMode gain compression/limiters AMGC[1:0] Mode User programmable GC AC no clipping AC limited clipping (10%) DRC nighttime listening mode 00 01 10 11 Table 52. Bit AMPS - AutoMode auto prescale RST Name Description AutoMode pre-scale 0: -18 dB used for pre-scale when AMEQ neq 00 1: user defined pre-scale when AMEQ neq 00 R/W 0 RW 0 AMPS 35/57 Register description STA328 6.8.2 AutoMode AM/pre-scale/bass management scale (addr 0x0C) D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0 Table 53. Bit AutoMode AM switching enable RST Name Description AutoMode AM enable 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings AM switching frequency setting Default: 000 R/W 0 RW 0 AMAME 3:1 n RW 000 AMAM[2:0] Table 54. AutoMode AM switching frequency selection 48 kHz/96 kHz input fs 0.535 MHz -0.720 MHz 0.721 MHz -0.900 MHz 0.901 MHz -1.100 MHz 1.101 MHz -1.300 MHz 1.301 MHz -1.480 MHz 1.481 MHz -1.600 MHz 1.601 MHz -1.700 MHz 44.1 kHz/88.2 kHz input fs 0.535 MHz -0.670 MHz 0.671 MHz -0.800 MHz 0.801 MHz -1.000 MHz 1.001 MHz -1.180 MHz 1.181 MHz -1.340 MHz 1.341 MHz -1.500 MHz 1.501 MHz - 1.700 MHz AMAM[2:0] 000 001 010 011 100 101 110 When DDX(R) is used concurrently with an AM radio tuner, it is advisable to use the AMAM bits to automatically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is receiving. The values used in AMAM are also dependent upon the sample rate determined by the ADC used. Table 55. Bit AutoMode crossover setting RST Name Description AutoMode crossover frequency selection 000: user defined crossover coefficients are used Otherwise: preset coefficients for the crossover setting desired R/W 7:4 RW 0 XO[3:0] Table 56. Crossover frequency selection Bass management - Crossover frequency User 80 Hz 100 Hz 120 Hz 140 Hz XO[2:0] 0000 0001 0010 0011 0100 36/57 STA328 Table 56. Crossover frequency selection (continued) Register description XO[2:0] 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz Bass management - Crossover frequency 6.8.3 Preset EQ settings (addr 0x0D) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 PEQ4 0 D3 PEQ3 0 D2 PEQ2 0 D1 PEQ1 0 D0 PEQ0 0 Table 57. Preset EQ selection Setting Flat Rock Soft rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-hop Dialog Bass-boost #1 Bass-boost #2 Bass-boost #3 Loudness 1 (least boost) PEQ[3:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 37/57 Register description Table 57. Preset EQ selection (continued) Setting Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost) STA328 PEQ[3:0] 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 6.9 6.9.1 Channel configuration registers Channel 1 configuration (addr 0x0E) D7 C1OM1 0 D6 C1OM0 0 D5 C1LS1 0 D4 C1LS0 0 D3 C1BO 0 D2 C1VBP 0 D1 C1EQBP 0 D0 C1TCB 0 6.9.2 Channel 2 configuration (addr 0x0F) D7 C2OM1 0 D6 C2OM0 0 D5 C2LS1 0 D4 C2LS0 0 D3 C2BO 0 D2 C2VBP 0 D1 C2EQBP 0 D0 C2TCB 0 6.9.3 Channel 3 configuration (addr 0x10) D7 C3OM1 0 D6 C3OM0 0 D5 C3LS1 0 D4 C3LS0 0 D3 C3BO 0 D2 C3VBP 0 D1 Reserved 0 D0 Reserved 0 EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. 38/57 STA328 Register description CxEQBP: " " 0 perform EQ on channel X - normal operation 1 bypass EQ on channel X Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed. CxTCB: " " 0 perform tone control on channel x - (default operation) 1 bypass tone control on channel x Each channel can be configured to output either the patented DDX(R) PWM data or standard binary PWM encoded data. By setting the CxBO bit to 1, each channel can be individually controlled to be in binary operation mode. Also, there is the capability to map each channel independently onto any of the two limiters available within the STA328 or even not map it to any limiter at all (default mode). Table 58. Channel limiter mapping selection Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 CxLS[1,0] 00 01 10 Each PWM Output Channel can receive data from any channel output of the volume block. Which channel a particular PWM output receives is dependent upon that channel's CxOM register bits. Table 59. Channel PWM output mapping CxOM[1:0] PWM output from Channel 1 Channel 2 Channel 3 Not used 00 01 10 11 39/57 Register description STA328 6.10 Tone control (addr 0x11) D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1 Table 60. Tone control boost/cut selection BTC[3:0]/TTC[3:0] Boost/Cut -12 dB -12 dB ... -4 dB -2 dB 0 dB +2 dB +4 dB ... +12 dB +12 dB +12 dB 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 40/57 STA328 Register description 6.11 6.11.1 Dynamics control Limiter 1 attack/release threshold (addr 0x12) D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0 6.11.2 Limiter 1 attack/release threshold (addr 0x13) D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1 6.11.3 Limiter 2 attack/release rate (addr 0x14) D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0 6.11.4 Limiter 2 attack/release threshold (addr 0x15) D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1 6.11.5 Dynamics control description The STA328 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in configuration register D (bit 5, address 0x03). Each channel can be mapped to Limiter1, Limiter2, or not mapped. If a channel is not mapped, that channel will clip normally when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. When the attack threshold has been exceeded, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. The gain can never be increased past its set value 41/57 Register description STA328 and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 17. Basic limiter and volume flow diagram Limiter RMS Gain/Volume Input Gain Attenuation Saturation Output Table 61. LxA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Limiter attack/release rate selection Attack rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Slow Fast LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Release rate dB/ms 42/57 STA328 Register description 6.11.6 Anti-clipping mode Table 62. LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10 Limiter attack/release threshold selection (AC mode) Attack threshold (AC) dB relative to FS LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 - -29 dB -20 dB -16 dB -14 dB -12 dB -10 dB -8 dB -7 dB -6 dB -5 dB -4 dB -3 dB -2 dB -1 dB -0 dB Release threshold (AC) dB relative to FS 43/57 Register description STA328 6.11.7 Dynamic range compression mode Table 63. LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4 Limiter attack/release threshold selection (DRC mode) Attack threshold (DRC) dB relative to volume LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Release threshold (DRC) db relative to volume + LxAT - -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB -9 dB -6 dB 44/57 STA328 User programmable processing 7 7.1 User programmable processing EQ - biquad equation The biquads use the equation that follows. This is diagrammed in Figure 18 below. Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n - 1] + b2X[n - 2] - 2(a1/2)Y[n - 1] - a2Y[n - 2] = b0X[n] + b1X[n - 1] + b2X[n - 2] - a1Y[n - 1] - a2Y[n - 2] where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). Coefficients stored in the user defined coefficient RAM are referenced in the following manner: " " " " " CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in the fourth biquad for channel 3 Figure 18. Biquad filter b0 /2 Z -1 b1 /2 Z -1 2 2 + Z -1 + 2 -a1 /2 Z -1 b2 + -a2 7.2 Pre-scale The pre-scale block which precedes the first biquad is used for attenuation when filters are designed that boost frequencies above 0 dBFS. This is a single 28-bit signed multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, all pre-scale factors are set to 0x7FFFFF. 7.3 Post-scale The STA328 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit. 45/57 User programmable processing STA328 7.4 Mix/bass management The STA328 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. These coefficients are accessible via the user controlled coefficient RAM described below. The mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608) are used to provide three channels of output from two channels of filtered input. Figure 19. Mix/bass management block diagram Channel #1 from EQ C1MX1 + Channel #2 from EQ High-Pass XO Filter Channel#1 to GC/Vol C1MX2 C2MX1 + High-Pass XO Filter Channel#2 to GC/Vol C2MX2 C3MX1 + Low-Pass XO Filter Channel#3 to GC/Vol C3MX2 User-defined Mix Coefficients Crossover Frequency determined by XO setting. User-defined when XO = 000 After a mix is achieved, STA328 also provides the capability to implement crossover filters on all channels corresponding to 2.1 bass management solution. Channels 1 and 2 use a first-order high-pass filter and channel 3 uses a second-order low-pass filter corresponding to the setting of the XO bits of I2C register 0x0C. If XO = 000, user specified crossover filters are used. By default these coefficients correspond to pass-through. However, the user can write these coefficients in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd order crossover filters. This output is then passed on to the volume/limiter block. 46/57 STA328 User programmable processing 7.5 Calculating 24-bit signed fractional numbers from a dB value The pre-scale, mixing, and post-scale functions of the STA328 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to +1. It is possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the equations below. " " " " Non-inverting phase numbers 0 to +1: Coefficient = round(8388607 * 10(dB / 20)) Inverting phase numbers 0 to -1: Coefficient = 16777216 - round(8388607 * 10(dB / 20)) As can be seen by the preceding equations, the value for positive phase 0 dB is 0x7FFFFF and the value for negative phase 0 dB is 0x800000. 7.6 7.6.1 User defined coefficient RAM Coefficient address register 1 (addr 0x16) D7 CFA7 0 D6 CFA6 0 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0 7.6.2 Coefficient b1data register bits 23:16 (addr 0x17) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 7.6.3 Coefficient b1data register bits 15:8 (addr 0x18) D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0 7.6.4 Coefficient b1data register bits 7:0 (addr 0x19) D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0 7.6.5 Coefficient b2 data register bits 23:16 (addr 0x1A) D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0 47/57 User programmable processing STA328 7.6.6 Coefficient b2 data register bits 15:8 (addr 0x1B) D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0 7.6.7 Coefficient b2 data register bits 7:0 (addr 0x1C) D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0 7.6.8 Coefficient a1 data register bits 23:16 (addr 0x1D) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 7.6.9 Coefficient a1 data register bits 15:8 (addr 0x1E) D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0 7.6.10 Coefficient a1 data register bits 7:0 (addr 0x1F) D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0 7.6.11 Coefficient a2 data register bits 23:16 (addr 0x20) D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0 7.6.12 Coefficient a2 data register bits 15:8 (addr 0x21) D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0 7.6.13 Coefficient a2 data register bits 7:0 (addr 0x22) D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0 48/57 STA328 User programmable processing 7.6.14 Coefficient b0 data register bits 23:16 (addr 0x23) D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0 7.6.15 Coefficient b0 data register bits 15:8 (addr 0x24) D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0 7.6.16 Coefficient b0 data register bits 7:0 (addr 0x25) D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0 7.6.17 Coefficient write control register (addr 0x26) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 Reserved 0 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0 Coefficients for EQ, mix and scaling are handled internally in the STA328 via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM. The following are instructions for reading and writing coefficients. 49/57 User programmable processing STA328 7.7 Reading a coefficient from RAM " " " " " write 8 bits of address to I2C register 0x16 write 1 to bit R1 (D2) of I2C register 0x26 read top 8 bits of coefficient in I2C address 0x17 read middle 8 bits of coefficient in I2C address 0x18 read bottom 8 bits of coefficient in I2C address 0x19 7.8 Reading a set of coefficients from RAM " " " " " " " " " " " " " " " " " write 8 bits of address to I2C register 0x16 write 1 to bit RA (D3) of I2C register 0x26 read top 8 bits of coefficient in I2C address 0x17 read middle 8 bits of coefficient in I2C address 0x18 read bottom 8 bits of coefficient in I2C address 0x19 read top 8 bits of coefficient b2 in I2C address 0x1A read middle 8 bits of coefficient b2 in I2C address 0x1B read bottom 8 bits of coefficient b2 in I2C address 0x1C read top 8 bits of coefficient a1 in I2C address 0x1D read middle 8 bits of coefficient a1 in I2C address 0x1E read bottom 8 bits of coefficient a1 in I2C address 0x1F read top 8 bits of coefficient a2 in I2C address 0x20 read middle 8 bits of coefficient a2 in I2C address 0x21 read bottom 8 bits of coefficient a2 in I2C address 0x22 read top 8 bits of coefficient b0 in I2C address 0x23 read middle 8 bits of coefficient b0 in I2C address 0x24 read bottom 8 bits of coefficient b0 in I2C address 0x25 7.9 Writing a single coefficient to RAM " " " " " write 8 bits of address to I2C register 0x16 write top 8 bits of coefficient in I2C address 0x17 write middle 8 bits of coefficient in I2C address 0x18 write bottom 8 bits of coefficient in I2C address 0x19 write 1 to W1 bit in I2C address 0x26 50/57 STA328 User programmable processing 7.10 Writing a set of coefficients to RAM " " " " " " " " " " " " " " " " " write 8 bits of starting address to I2C register 0x16 write top 8 bits of coefficient b1 in I2C address 0x17 write middle 8 bits of coefficient b1 in I2C address 0x18 write bottom 8 bits of coefficient b1 in I2C address 0x19 write top 8 bits of coefficient b2 in I2C address 0x1A write middle 8 bits of coefficient b2 in I2C address 0x1B write bottom 8 bits of coefficient b2 in I2C address 0x1C write top 8 bits of coefficient a1 in I2C address 0x1D write middle 8 bits of coefficient a1 in I2C address 0x1E write bottom 8 bits of coefficient a1 in I2C address 0x1F write top 8 bits of coefficient a2 in I2C address 0x20 write middle 8 bits of coefficient a2 in I2C address 0x21 write bottom 8 bits of coefficient a2 in I2C address 0x22 write top 8 bits of coefficient b0 in I2C address 0x23 write middle 8 bits of coefficient b0 in I2C address 0x24 write bottom 8 bits of coefficient b0 in I2C address 0x25 write 1 to WA bit in I2C address 0x26 The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (for example 0, 5, 10, 15, ..., 45 decimal), and the STA328 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. Table 64. RAM block for biquads, mixing, and scaling Index (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x13 0x14 Channel 2 - Biquad 1 21 ... 39 0x15 ... 0x27 ... Channel 2 - Biquad 4 C2H11 ... C2H44 0x000000 ... 0x400000 Channel 1 - Biquad 2 ... Channel 1 - Biquad 4 Channel 1 - Biquad 1 Coefficient C1H10 (b1/2) C1H11 (b2) C1H12 (a1/2) C1H13 (a2) C1H14 (b0/2) C1H20 ... C1H44 C2H10 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 ... 0x400000 0x000000 Index (decimal) 0 1 2 3 4 5 ... 19 20 51/57 User programmable processing Table 64. RAM block for biquads, mixing, and scaling (continued) Index (Hex) 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Channel 1 - Pre-scale Channel 2 - Pre-scale Channel 1 - Post-scale Channel 2 - Post-scale Channel 3 - Post-scale Thermal warning - Post scale Channel 1 - Mix 1 Channel 1 - Mix 2 Channel 2 - Mix 1 Channel 2 - Mix 2 Channel 3 - Mix 1 Channel 3 - Mix 2 Unused Unused Low-pass 2nd order filter for XO = 000 High-pass 2nd order filter for XO = 000 Coefficient C12H0 (b1/2) C12H1 (b2) C12H2 (a1/2) C12H3 (a2) C12H4 (b0/2) C12L0 (b1/2) C12L1 (b2) C12L2 (a1/2) C12L3 (a2) C12L4 (b0/2) C1PreS C2PreS C1PstS C2PstS C3PstS TWPstS C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2 STA328 Index (decimal) 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x5A9DF7 0x7FFFFF 0x000000 0x000000 0x7FFFFF 0x400000 0x400000 52/57 STA328 User programmable processing 7.11 Variable max power correction (addr 0x27, 0x28) D7 MPCC15 0 MPCC7 1 D6 MPCC14 0 MPCC6 1 D5 MPCC13 1 MPCC5 0 D4 MPCC12 0 MPCC4 0 D3 MPCC11 1 MPCC3 0 D2 MPCC10 1 MPCC2 0 D1 MPCC9 0 MPCC1 0 D0 MPCC8 1 MPCC0 0 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 7.12 Fault detect recovery (addr 0x2B, 0x2C) D7 FRDC15 0 FDRC7 0 D6 FDRC14 0 FDRC6 0 D5 FDRC13 0 FDRC5 0 D4 FDRC12 0 FDRC4 0 D3 FDRC11 0 FDRC3 1 D2 FDRC10 0 FDRC2 1 D1 FDRC9 0 FDRC1 0 D0 FDRC8 0 FDRC0 0 FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the output TRISTATE will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 1 ms. 53/57 Package mechanical data STA328 8 Package mechanical data Figure 20. PowerSO-36 slug up outline drawing 54/57 STA328 Table 65. Symbol Min A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L M N R s 3.25 3.10 0.80 0.03 0.22 0.23 15.80 9.40 13.90 10.90 5.80 2.90 0 15.50 0.80 2.25 0.20 1.00 0.65 11.05 0.6 Typ 3.43 3.20 1.00 -0.04 0.38 0.32 16.00 9.80 14.50 11.10 2.90 6.20 3.20 0.08 15.90 1.10 1.10 2.60 10 degrees 8 degrees Max Min 0.128 0.122 0.031 0.001 0.009 0.009 0.622 0.370 0.547 0.429 0.228 0.114 0 0.610 0.031 0.089 - Package mechanical data PowerSO-36 slug up dimensions mm inch Typ 0.008 0.039 0.026 0.435 0.024 Max 0.135 0.126 0.039 -0.002 0.015 0.013 0.630 0.386 0.571 0.437 0.114 0.244 0.126 0.003 0.626 0.043 0.043 0.102 10 degrees 8 degrees In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 55/57 Revision history STA328 9 Revision history Table 66. Date Sep-2004 Jul-2005 May-2006 Document revision history Revision 1 2 3 Initial release Added pins 7 and 25 in block diagram Changed from product preview to maturity Updated device pin 1 labeling and connections Updated applications schematic Figure 5 on page 7 Added characterization curves in Chapter 4 on page 14 Updated device address in Section 5.2 on page 16 Updated configuration registers in Table 9: Register summary on page 19 Updated configuration registers from Section 6.1 on page 20 to Section 6.5 Updated PowerSO-36 Package mechanical data on page 54 Changes 13-May-2008 4 56/57 STA328 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 57/57 |
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